JPS6351296B2 - - Google Patents

Info

Publication number
JPS6351296B2
JPS6351296B2 JP58169945A JP16994583A JPS6351296B2 JP S6351296 B2 JPS6351296 B2 JP S6351296B2 JP 58169945 A JP58169945 A JP 58169945A JP 16994583 A JP16994583 A JP 16994583A JP S6351296 B2 JPS6351296 B2 JP S6351296B2
Authority
JP
Japan
Prior art keywords
resident area
area
resident
tag information
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58169945A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6061844A (ja
Inventor
Hideo Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58169945A priority Critical patent/JPS6061844A/ja
Publication of JPS6061844A publication Critical patent/JPS6061844A/ja
Publication of JPS6351296B2 publication Critical patent/JPS6351296B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58169945A 1983-09-14 1983-09-14 キヤツシユ制御方式 Granted JPS6061844A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58169945A JPS6061844A (ja) 1983-09-14 1983-09-14 キヤツシユ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58169945A JPS6061844A (ja) 1983-09-14 1983-09-14 キヤツシユ制御方式

Publications (2)

Publication Number Publication Date
JPS6061844A JPS6061844A (ja) 1985-04-09
JPS6351296B2 true JPS6351296B2 (en]) 1988-10-13

Family

ID=15895795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58169945A Granted JPS6061844A (ja) 1983-09-14 1983-09-14 キヤツシユ制御方式

Country Status (1)

Country Link
JP (1) JPS6061844A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01173696U (en]) * 1988-05-20 1989-12-08

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559201A (en) * 1978-06-30 1980-01-23 Fujitsu Ltd Buffer memory control system
JPS5619571A (en) * 1979-07-23 1981-02-24 Nec Corp Buffer memory unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01173696U (en]) * 1988-05-20 1989-12-08

Also Published As

Publication number Publication date
JPS6061844A (ja) 1985-04-09

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